AMERICOM SEMINARS PRESENTS THE HIGH SPEED DIGITAL DESIGN and EMI/EMC COURSES Increasingly fast microprocessors cause coupling, crosstalk, EMI and signal integrity dilemmas in today’s PCB designs. Join us for a course that gives engineers and designers the ability to properly design at CAE and CAD to control clock loading and eliminate transmission line effects; to select the tool set to ease the design process; and to describe the issues of the PCB: stack up, laminate choice, and embedded components. In this e-mail, find the following 1. ON-SITE SEMINAR INFORMATION 2. BENEFITS OF ATTENDING THE SEMINARS 3. INSTRUCTOR FOR THE SEMINARS 4. HIGH SPEED DIGITAL DESIGN COURSE OUTLINE 5. KEY ISSUES OF EMI/EMC COURSE OUTLINE 6. REGISTRATION INFORMATION ________________________________________________________________________ COPY THIS E-MAIL--CLICK EDIT, SELECT ALL, CLICK EDIT, COPY, AND THEN PASTE INTO AN E-MAIL THAT YOU SEND FORWARD THESE COURSES TO YOUR COLLEAGUES--E-MAIL THEM THIS INFORMATION! * Digital design engineers * Design managers * Test engineers * EMI/EMC engineers * IC digital logic designers * Project managers of high-speed designs ________________________________________________________________________ ______________________________ 1. SEMINAR LOCATIONS AND DATES ______________________________ ARRANGE A SEMINAR AT YOUR LOCATION Contact us to make arrangements at americomseminars@aol.com ATTEND A PUBLIC SEMINAR HOSTED AT AN AREA NEAR YOU Check www.americomseminars.com for the latest seminar locations and dates ______________________________________ 2. BENEFITS OF ATTENDING THE SEMINARS ______________________________________ THESE COURSES WILL HELP YOU · Control Clock Loading · Eliminate Transmission Line Effects · Solve signal integrity dilemmas · Design High speed PCB right the first time · Ensure your PCB meets your high speed requirements · Be aware of EMI/EMC problems HAVE YOU THOUGHT THIS? “We have a problem with the layout of a board.” “My job requires more knowledge about high speed design.” “I’m facing design issues.” “I have intuition about high speed issues but little solid knowledge.” “My company has high speed digital PCBs.” “I want a refresher course to review fundamentals and learn new stuff.” “I want to learn new info that I can’t get by solely depending on my office.” “Our customers use a high speed interface.” “Our company needs to keep up with expanding technology.” “We encounter signal integrity issues requiring high frequency solutions.” “I hope to learn valuable information quicker than I would on-the-job.” “The designs keep getting faster and faster.” THESE COURSES WILL BENEFIT YOU The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have broken the 50ps barrier. This has resulted in high-speed design problems such as: · A lack of control over impedance and reflections · Crosstalk and bypassing failures · Time delays, false triggering and reflections · Failure to meet EMI and FCC requirements It is the edge rate, not the frequency, which exacerbates this problem. So, even if your design is for moderate frequency, the edge rates can cause these designs to reflect the high-speed effects. Most designs today use a microprocessor and today’s micros have clock rates about 400 times higher than the original 8 and 16 bit machines. A key factor is the minimization of the semiconductor device (now at .12 mm) leading to less parasitic L and C and thereby faster switching rates. This phenomenon is also apparent in RAMs, ROMs, ASICs and Gate Arrays. This leads to PCBs requiring terminators, new CAD routing disciplines, and component additions to minimize ground bounce effects. More and more designs are requiring these faster devices to meet more demanding specifications that match or beat the competition. The purpose of this course is to provide you with the knowledge to do it right the first time. The course provides tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. The course emphasizes cost competitive design without sacrificing high-speed integrity. ________________________________ 3. INSTRUCTOR FOR THESE COURSES ________________________________ “Mr. Hanson is well spoken, patient, knowledgeable . . . gives practical examples.” “(I)nstructor’s presentation was superb. Very good job of connecting electronics to the real world.” “The course was excellent. Hanson demystified high speed.” Participants in Mr. Hanson’s courses Robert Hanson, MSEE, is President of Americom Seminars, Inc. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and Loral, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. Mr. Hanson has taught high-speed digital design courses throughout the United States, Europe and Asia. He has presented electrical engineer courses at all Nepcon conferences, University of California–Berkeley, University of Wisconsin, University of Oxford-England, IPC, and SAE. He has also done on-site private consultations and training sessions for over eighty companies in the United States and internationally. Robert Hanson teaches and consults for 3-Com, Advanced Fibre Communications, Alcatel, Allied Signal, Apple, AT&T, Boeing, Chrysler, Cisco, Compaq, Cray, da Vinci Systems, Data Device, Dell, Delphi, Ford, Gateway, GE, Gen Rad, Honeywell, HP, IBM, Intel, Lockheed, Lucent, Marconi, Micron, Motorola, NEC, eLuminant, Nortel, Panasonic, Qualcomm, Rockwell, Samsung-Korea, Solectron, Storage Tek, Sun, Tektronix, Teradyne, TI, TRW, Tycom Laboratories, Xerox, and Xilinx REGISTER AT www.americomseminars.com ____________________________________________ 4. HIGH SPEED DIGITAL DESIGN COURSE OUTLINE ____________________________________________ The high speed course is for anyone who has worked with today’s ICs, high-speed designs and PCB layouts. No advanced math is required though attendees will find it helpful to bring a scientific calculator to the course. The course is not an introductory course. It is presented at a technical level that will provide experienced designers with information to design and layout a high speed PCB. FUNDAMENTALS Frequency and Time Time and Distance Lumped Versus Distributed Systems Four Kinds of Reactance Ordinary Capacitance and Inductance Mutual Capacitance & Inductance HIGH-SPEED PROPERTIES OF LOGIC GATES Quiescent vs. Active Dissipation Driving Capacitive Loads Input Power and Internal Power TTL, CMOS, ECL, & GaAs Output Power Speed and engineering disciplines Dv, di effects and Voltage Margins Ground Bounce and Lead Inductance Electronic Packages: QFPs, PGAs, SOIC, PLCC, BGA, COB, TAB, FC, CSP and their relationship to SI Lead Capacitance Thermal Considerations MEASUREMENT TECHNIQUES Rise Time and Bandwidth of Oscilloscope Probes Self-inductance of a Probe Ground Loop Spurious Signal Pickup from Probe Ground Loops How Probes Load Down a Circuit Special Probing Fixtures Avoiding Pickup from Probe Shield Currents Viewing a Serial Data Transmission System PLL and DLLs and eye patterns Communications - SONET, SERDES, OC 192/768, Fiber Slowing Down the System Clock Observing Crosstalk Measuring Operating Margins Observing Metastable States in Flip-Flops TRANSMISSION LINES Shortcomings of wirewrap (Q, EMI, crosstalk) Infinite Uniform Transmission Line Effects of Source and Load Impedance Special Transmission Line Cases Line Impedance & Propagation Delay Skin/proximity effect Matching Z0 with trace alturations Characteristics of T. lines: coax, pair, m strip, stripline and differential: asymmetric, dual, edge. TERMINATIONS End/Source/Middle Terminators AC Biasing for End Terminators Diode and active terminators Resistor Selection (why 0201s) Crosstalk in Terminators VIAS Mechanical Properties of Vias Capacitance & Inductance of Vias Return Current and Its Relation to Vias Through Hole, Blind, Buried, and Micro Vias Intelligent Vias and autorouters GROUND PLANES AND LAYER STACKING High-Speed Current Follows the Path of Least Inductance Crosstalk in Solid Ground Planes, Slotted Ground Planes, and Cross-Hatched and Ground Fingers Guard Traces Near-End and Far-End Crosstalk Separating analog from digital, ECL/PECL from TTL/CMOS the concept of moats/floats/drawbridge How to Stack Printed Circuit Board Layers (e.g. 4, 6, and 10 layer) SIR vs. frequency, software for performing crosstalk and ground bounce tests POWER SYSTEMS Providing a stable Voltage Reference Distributing Uniform Voltage Everyday Distribution Problems Choosing a Bypass Capacitor Power plane resonance Designing a bypass system CONNECTORS AND CABLES Mutual Inductance – How Connectors Create Crosstalk Series Inductance-How Connectors Create EMI Parasitic Capacitance—Using Connectors on a Multidrop Bus (Z mismatch reflection) Measuring Coupling in a Connector Continuity of Gnd Underneath a Connector Fixing EMI with External Connections Special Connectors for High-Speed requirements Differential Signaling Through a Connector BUSES Multidrop systems: Drivers, Transceivers, PCI, BTL, GTL & RAMBUS How they function, Clock rates, typical failures LVDS: types, unbalance, noise, layout and how to make them function CLOCK DISTRIBUTION/OSCILLATION Timing Margin Clock Skew Using Low-Impedance Drivers and Clock Distribution Lines Source Termination of Multiple Clock Lines Controlling Crosstalk on Clock Lines Delay Adjustments Differential Distribution Clock Signal Duty Cycle Using Canned Clock Oscillators Clock Jitter (edge, cycle, long term) Source synchronous clocking, DDR & RDRAM Spread spectrum clocking for EMI control: Does it work? THE PCB Dielectric Constant and Dissipation Factor FR4, Teflon (PFTE) and Substitution Materials Layer Stackups, Power, Ground, and Signal Planes Tradeoffs of R, C, L, and Manufacturing Concerns Plating, Vias, CAM for Fast Turnaround HIGH SPEED DEVELOPMENT TOOLS Signal Integrity Tools Routing and Placement Timing Analysis PRACTICAL As the seminar progresses, Mr. Hanson presents a design for two perfect SI PCBs, single and differential. The designs will address issues such as transmission line reflection, ground bounce, ground and V plane layout, crosstalk, via requirements, bypassing connectors, EMI, and CLK control. HIGH SPEED EXHIBITS For all three days, examine on-display high speed PCBs, components, and populated PCBs with magnifiers for observing flip chips, chip on board, tape automatic bonding, chip scale packages, BGAs, and multichip modules. Also, view traditional PCBs and components (SOICs, PLCCs, PGAs, QFPs, and TSOPs). SIGNAL INTEGRITY DEMO Observe demonstrations of high speed PCB simulation on a PC/overhead format on the second night of the seminar. This setting will provide an excellent opportunity for students to interchange ideas, problems, and solutions. _______________________________________________________________________________________ 5. KEY ISSUES OF EMI/EMC COURSE OUTLINE _______________________________________________________________________________________ This course is targeted for electrical engineers who are responsible for providing a design that meets Signal Integrity (SI) and EMI. If you are an EE, you want to know why EMI testing is done, how it is conducted, and what the typical failures are, even if a special department or an outside EMI company does the actual testing. This course gives you the EMI information you need including design considerations at both CAE and CAD to provide a compliant radiation/susceptibility product. You’ll examine and identify ways to prevent common EMI/EMC problems regarding power supplies, cables, connectors, slots, discontinuity of ground planes and antenna loops. TOPICS COVERED IN THE COURSE · EMI, Source, path and receptor. EMI regulations – standards for USA, Europe (EU), and Asia. · ESD and Power Disturbances · RFI, EMI regarding PCBs, computers, analog designs and systems · ICs, Rs, Cs, dv/dt, di/dt; EMI and PCB stackups · Controlling EMI with shielding · Cables and connectors (the big offenders) · Grounding · Troubleshooting EMI problems in the factory or field ____________________________ 6. REGISTRATION INFORMATION ____________________________ INFORMATION NEEDED FOR REGISTRATION E-mail this info to us at americomseminars@aol.com or fax it to us at 775-883-2384 You can register right at www.americomseminars.com if you prefer! Pick your seminar ___ I am interested in an on-site, private seminar; please contact me ___ I am interested in EE for Non-EE courses Provide this information Your name Your job title Your company/organization Your address with city, state, and zip code Your work phone number (with area code) Your fax number (with area code) Your e-mail address Pay with _____ Check-Money Order (enclosed) Pay with _____ Mastercard _____ VISA _____ Am. Express _____ Discover ______ P.O. Provide Credit Card or PO Number State credit card expiration date State credit card billing address with zip code If you wish, include a note stating the main high-speed concern at your company. FIVE WAYS TO ENROLL E-mail: E-mail us the information requested above to americomseminars@aol.com Web: Register at www.americomseminars.com Fax: Fax the form to 1-775-883-2384 Phone: Call 1-800-650-3033; please have your credit card available or a P.O. number (outside US, call 360-479-0949) Mail: Mail the form to Americom Seminars, Inc.; 2533 No. Carson Street, Suite 4213; Carson City NV 89706 If you have not received confirmation of your enrollment within 7 working days of sending your registration, please e-mail us at americomseminars@aol.com See our web page for fees. www.americomseminars.com For other locations, contact us at: americomseminars@aol.com   The three day fee includes the following for each student: Three full days of instruction covering the most critical and salient aspects of high speed design and troubleshooting and  A copy of High-Speed Digital Design: A Handbook of Black Magic by Howard Johnson, Ph.D. and Martin Graham, Ph.D. Comprehensive, 370+ page book of class notes Exhibits for viewing Certificate of Completion indicating your participation in the course The four day fee also includes  Two additional days of instruction covering EMI/EMC issues A comprehensive set of course notes and the 299-page book, EMC for Product Designers, by Tim Williams.   Students at public seminars also receive  Continental breakfast, lunch, and refreshments daily Firms that send three or more attendees to public seminars receive a $75 discount per person for 3-day seminars; $100 per person for 4-day seminars. PAYMENT · Checks or Money Orders made to Americom Seminars, Inc. · VISA, MasterCard, American Express, Discover · Purchase Orders; 10% fee for P.O.’s, waived if paid within 30 days of the invoice date. CANCELLATIONS You may cancel your enrollment up to 15 days prior to the seminar, but you must pay a $100 processing fee. Cancellations 2 to 14 days before the seminar pay a $250 fee ($150 for 1 day class). Cancellations the day before or day of the seminar, owe the full amount. You may substitute enrollees at any time. If this course is not held for any reason, Americom Seminars, Inc.’s liability is limited to refund of the full course fee. Questions: Email us at americomseminars@aol.com Call us at 1-800-650-3033 (outside U.S., call 360-479-0949) Write us at: Americom Seminars; 2533 North Carson Street Suite 4213; Carson City NV 89706 CERIFICATE OF COMPLETION You will be presented with a certificate indicating your completion of this course. SCHEDULE Registration: 8:00 - 8:30 am (first day only) Lectures: 8:30 am – 12:30 pm Lunch: 12:30 – 1:30 pm Lectures: 1:30 – 5:00 pm Demos on the second night of the seminar occur from 5:15 to 8:00 pm if the vendor is available. QUESTIONS Email us at americomseminars@aol.com Call us at 1-800-650-3033 (outside U.S., call 360-479-0949) Write us at: Americom Seminars, Inc.; 2533 North Carson Street Suite 4213; Carson City NV 89706