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Robert Hanson, M.S.E.E.,
President, Americom Seminars, Internationally
Recognized Expert with over 35 years of experience. Americom Seminars has provided outstanding
electrical engineering seminars for over 16 years! Mr.
Hanson teaches a variety of courses. High Speed Brochure to
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Choose
the seminar you are interested in for more information. Mr.
Hanson will present to your company on your schedule. One person, several people,
many people can attend; Mr. Hanson can present on ANY day of the week and can
present during the mornings, afternoons, and evenings. |
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HIGH SPEED DIGITAL DESIGN SEMINARS Increasingly fast microprocessors cause coupling, crosstalk,
EMI and signal integrity dilemmas in today’s PCB designs. Join us for a
seminar that gives engineers
and designers the ability to properly design at CAE and CAD to control clock
loading and eliminate transmission line effects; to select the tool set to
ease the design process; to describe the issues of the PCB: stack up,
laminate choice, and embedded components; and EMI/EMC information you need
including design considerations at both CAE and CAD to provide a compliant
radiation / susceptibility product. Got questions about a seminar at your location? Info about having a seminar at your site! Email us at americomseminars@aol.com Benefits of attending the High Speed Digital Design Seminars The speed of today’s
logic devices mandates that the interconnects on
PCBs must meet the high switching rise/fall times of these devices. Switching
edges are in the 200ps to 300ps range and some devices have edges that have
broken the 50ps barrier. This has resulted in high-speed design problems such
as: ·
A
lack of control over impedance and reflections ·
Crosstalk
and bypassing failures ·
Time
delays, false triggering and reflections ·
Failure
to meet EMI and FCC requirements It is the edge rate, not
the frequency, which exacerbates this problem. So, even if your design is for
moderate frequency, the edge rates can cause these designs to reflect the
high-speed effects. Most designs today use a microprocessor and today’s
micros have clock rates about 400 times higher than the original 8 and 16 bit
machines. A key factor is the minimization of the semiconductor device (now
at .12 mm) leading to less
parasitic L and C and thereby faster switching rates. This phenomenon is also
apparent in RAMs, ROMs, ASICs
and Gate Arrays. This leads to PCBs requiring terminators, new CAD routing
disciplines, and component additions to minimize ground bounce effects. More
and more designs are requiring these faster devices to meet more demanding
specifications that match or beat the competition. The course provides you with the knowledge to do it right the first time. The course provides tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. The course emphasizes cost competitive design without sacrificing high-speed integrity. Got questions about a seminar at your location? Info about having a seminar at your site! Email us at americomseminars@aol.com High Speed Digital Design and PCB Layout Course Outline This course is for anyone who has worked with today’s ICs, high-speed designs and PCB layouts. No advanced math is required though attendees will find it helpful to bring a scientific calculator to the course. The course is not an introductory course. It is presented at a technical level that will provide experienced designers with information to design and layout a high speed PCB. Fundamentals Frequency, Time and Distance Lumped Versus Distributed Systems Four Kinds of Reactance Ordinary and Mutual Capacitance &
Inductance EM Fields Geometry, C, L, & Zo, interrelationships C & L Resonance
BGA:
Mr. Hanson discusses how to route at CAE/CAD so that the balls can be
paralleled to minimize L. The pads are NSMD and 8 mils vias
are on stringers. If done right, this is a very good high-speed device. High-Speed Properties of Logic Gates Quiescent vs. Active Dissipation Driving Capacitive Loads Input Power and External Power TTL, CMOS, SiGe,
In Pn, ECL, & GaAs;
Output Power, Speed and engineering disciplines, Dv,
di effects and Voltage Margins ICs: Cu vs
Al, what are the issues? Low K Di-electrics Intersymbol Interference (ISI), eye diagrams and
jitter Shoot Through Current (SSO) and how
to minimize it Ground Bounce, Lead Inductance,
Simultaneous Switching Noise (SSN) Electronic Packages: QFPs, PGAs, SOIC, PLCC, BGA,
COB, TAB, FC, CSP and their relationship to SI Lead Capacitance and Thermal
Considerations Measurement Techniques Rise Time and Bandwidth of
Oscilloscopes and probes Self-inductance and Spurious Signal
Pickup of a Probe Ground Loop How Probes Load Down a Circuit Special Probing Fixtures Avoiding Pickup from Probe Shield
Currents Viewing a Serial Data Transmission
System, the eye pattern closure ISI, Skin effect and tan loss. PLL and DLLs Communications - SONET, SERDES, OC
192/768, Fiber Slowing Down the System Clock Observing Crosstalk Measuring Operating Margins Observing Metastable
States in Flip-Flops “Excellent content. Bob
Hanson is very knowledgeable but most importantly he explains how things
work.” Participant in one of Mr. Hanson’s seminars. Transmission Lines The quality factor, Q, and why lumped
circuits can ring and cause EMI. Infinite Uniform Transmission Line Effects of Source and Load Impedance Special Transmission Line Cases Determining Line Impedance &
Propagation Delay using TDR and VNA Skin/proximity effect &
Dielectric Loss The Capacitive Load - Zo and propagation delay Matching Z0 with trace alturations
(neckdowns) – minimizing the 900, 450 bends
– are they concerns? Characteristics
of T. lines: coax, pair, micro
strip, buried micro strip, stripline &
differential: asymmetric, dual, edge. Even/odd, differential/common modes
are their effects on LVDS. “Very good anecdotes.” “Real-world examples used to help explain.” “Exceptional seminar (on high speed).” Participants in the course Terminations End/Source/Middle Terminators AC Biasing for End Terminators, where
should it be used and how to choose the capacitor Hairball networks, bifurcated lines
and capactive stubs Terminating differentials – Eliminating
common mode and minimizing power What causes differentials unbalance? Diode and active terminators,
Resistor Selection and Crosstalk in Terminators Vias Mechanical Properties of Vias Capacitance & Inductance of Vias Return Current and Its Relation to Vias Through Hole, Blind, Buried, Micro Vias Intelligent Vias
and autorouters Via discontinuity and via resonance
concerns Ground Planes and Layer StackingHigh-Speed Current Follows the Path
of Least Inductance Crosstalk in Solid and Slotted Ground
Planes Inductive/capacitive ratios for micro
strips, striplines, and asymmetric, dual, and edge
LVDS Guard Traces – Do they stop
crosstalk, can they resonate? Near-End and Far-End Crosstalk Separating analog from ECL/PECL and
TTL/CMOS the concept of moats/floats/drawbridge Split planes - CMOS/TTL, PECL and
analog using the same bias voltages How to Stack Printed Circuit Board
Layers (e.g. 4, 6, and 10 layer) for Zo
and crosstalk control, Cu fills on signal layers, minimizing warpage Interplane Capacitance – How thin, what
material and stackup placement SIR
vs. frequency, software for performing crosstalk and ground bounce tests “I know several people
who would really benefit from this.” Power Systems Providing a stable Voltage Reference
– Cu planes Distributing Uniform Voltage – Sense
lines, bulk C and interplane C Choosing a Bypass Capacitor –
Electrolytic/tantalum and ceramic Power plane resonance – serial and
parallel, how to minimize both Designing a .1 ohm bypass system up
to Fknee Designing for constant ESR IC die capacitance, discrete C in the
IC package Why the 0201 – Both for better
bypassing and EMI control Minimizing L-Capacitor layouts for SOICs, PLCCs, and various
configurations of BGAs Connectors & Cables Mutual and Series Inductance – How
Connectors Create Crosstalk Using Connectors on a Multidrop Bus (Z mismatch reflection) and how to match Zc to Zo,
Measuring Coupling in a Connector Continuity of Gnd
Underneath a Connector Special Connectors for High-Speed
requirements – Crosstalk and matching Zo
Differential Signaling Through a
Connector
PCMCIA:
Mr. Hanson discusses substitution materials instead of FR4 to control
capacitance. This will address its 3 mils/layer with fine lines which makes
it hard to control Z0 and causes crosstalk. Buses Multidrop systems: Drivers, Transceivers, PCI,
BTL, GTL & RAMBUS How they function, Clock rates,
typical failures ISI – Minimize the effect with
Equalization and Preemphasis LVDS: types, unbalance, noise, layout
& making them function Methods to speed up busses –
Distributive driving and load capacitance matching Clock Distribution Timing Margin and Clock Skew Using Low-Impedance Drivers and Clock
Distribution Lines Source Termination of Multiple Clock
Lines Controlling Crosstalk on Clock Lines Delay Adjustments – Serpentine
traces/DACs and varisters
for dynamic delay Differential Distribution Controlling Clock Signal Duty Cycle
using the integrator Source synchronous clocking, DDR & RDRAM
Got questions about a seminar at your location? Info about having a seminar at your site! Email us at americomseminars@aol.com
Comments
about the web pages, contact Jim Hanson at hansonjb@gmail.com
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Americom Seminars provides exceloin us at an Americom Seminar!
Comments
about the web pages, contact Jim Hanson at hansonjb@gmail.com |