TEST SEMINAR As the trend toward increased PCB complexity continues, there is a growing need to address testing issues at increasingly earlier stages of the design process. With high-density boards comes the challenge of 1GHZ device speeds and reduced physical access for testing, fault diagnosis and repair. Manufacturing high-quality reliable products requires concentrated effort in two closely related areas: · Maintaining tight control of manufacturing process to achieve high first time yields. · Developing an overall test strategy that provides both early fault detection and feedback of failure data to identify root causes of product defects. Throughout this three-day workshop, attendees will benefit from the instructor's extensive "real-world" experience as a test engineer and technical consultant. The format is designed to provide a number of excellent opportunities for students to seek answers to their unique SMT testing questions. OBJECTIVES · To show how PC board design choices affect test strategy implementation · To demonstrate proven concurrent engineering approaches to PC board design and layout issues that cut overall testing costs · To provide test-based tools to identify the causes of manufacturing defects in SMT assemblies WHAT YOU WILL LEARN · How to test bareboards with blind and buried vias and controlled impedance requirements. · What causes PCB contamination dendrites and how to test for it? · How to define In-Circuit Test requirements at schematic capture and PCB layout that insure adequate fault isolation and reduced functional test cost. · How to implement an overall test strategy to test early - test for less cost and minimize the need for functional test. · Ability to recognize deficiencies in both schematic capture and PCB layout that, when corrected, will greatly enhance the testability of your designs. · Awareness of the concerns of SMT Testing. · Bed-of-nails techniques for interfacing with very small pads and vias. · Best method of detecting manufacturing defects using either bed-of-nails, vision, or flying probe. · An introduction to vectorless testing used to detect shorts, opens, and other types of defects on high pin out areas of PCBs. WHO SHOULD ATTEND This seminar is designed for engineers and their managers involved in the manufacture of SMT and mixed technology electronic assemblies. It will be beneficial to engineering personnel responsible for: · Electrical Design and PCB Layout · Process and Manufacturing Engineering · Test Engineering · Quality Control/Quality Assurance. "Very good anecdotes." "Real-world examples used to help explain." "Bob Hanson is very knowledgeable but most importantly he explains how things work." Participants in Mr. Hanson's courses COURSE OUTLINE, TEST SEMINAR DAY 1 MORNING Schematic Capture Test Issues Board-level guides: initialization, signal monitoring, feedback, oscillator control, and ambiguity groups; LSI/VLSI test guides: partitioning and bus visibility, software/hardware control, controlling microprocessors, three-state buses, memory elements, synchronization, and clock control-examples of controlling CPU architectures for in-circuit test; mechanical testability guides: accessibility, board layout and board orientation, standard grids, design for simplicity/assembly/manufacturabilty; Analog and hybrid guides: signal interfacing, analog test points and partitioning analog circuitry; Scoring testability: three methods for scoring design testability and identifying areas of untestable designs. Routing Board Layout Design Issues Board size, parts placement, large components, test pads, vias, standard cells, auto drill/probe, and wire wrap issues; Spacing, skewing error sources, actual pad size, chip shooters, vision systems, coplanarity; CAD drill tapes, top/bottom side registration issues, tooling holes accuracy requirements, test probes, daughter boards, clam shell fixtures, test top modules, the lattice probe structure. DAY 1-AFTERNOON Bareboard Test Issues Effect of discrete components, SMT, and both buried and distributive capacitance on EMI, stripline and impedance controlled boards, and curved traces; Testing blind and buried vias; Bareboard test issues for high-density routing: resistance, frequency, and signal quality; Today's bareboard test capabilities: megohm level, safety features, speed fixturing enhancements and programming; Automation techniques for transferring router (data set) files directly to the B/B tester (i.e., eliminating software coding); Flying probe testing and the concept of rapid prototypes (i.e., testing just-in-time). Student Participation: A variety of boards will be displayed to illustrate concerns of testing bareboards. Also, videos will be presented showing methods of performing clam shell and flying probe bareboard test. DAY 2- In-Circuit Issues Standard cells and the ability to via electrical nodes: No-clean solder paste and ICT bed-of-nails (BON) contamination, vias under components-pros and cons; Purpose of 100% nodal visibility to the bottom of the board; Design rule checker requirements; Testing ASICs and MCMs; Board stress: what it is and how to eliminate it; test pad size: fixture tolerances, pin tolerances, and error sources in the B/B; Standard guides for automatic BONs fixturing; Why test spares; Detection of the fault cause: solder, components, printing, chip shooting, cleaning, and the human element-ICT must detect the fault, isolate the fault, and define the fault cause; Backdriving: requirements for CPU bus architectures, ASICs, and active components; What to do when the IC model is not in the library; Why intelligent ICT is the best SPC tool in the factory; What's new in wireless fixtures, magnetic plate, capacitive plate and reverse diode testing-how they work and what they can do for your company's ICT test capability; Can a board level functional test be completely eliminated; industry examples. Student Participation: A variety of populated PCBs and videos will be used to reflect the concerns of testing PCBs with today's high-density requirements. DAY 3 Board Contamination What causes it and what are the effects in electrical degradation, moisture absorption, and corrosive ionics; Surface insulation resistance: how to test it, defining acceptable limits; Ionograph testing, copper mirror test, solder mask corrosion test, and solderablity test: what they are and when they should be used. Vision Types: Microscope, X-ray, laser, AOI and laminography. What can they test, where should they be used and how they can affect ppm defects. Flying Probe (FP) Speed, accuracy, capabilities, testing BGA, CSP, TAB, FC, and COB using FP. Emerging Technology packages, videos and X8 magnifiers will be used to illustrate the need for Vision and Flying Probe. IEEE 1149.1 Boundary SCAN Why boundary SCAN: the ever-increasing electrical node-I/O pin visibility ratio and increasing lack of coverage using bed of nails; Understanding the spec: TAP control, data instruction registers, the five test instruction, running BIST; SCAN for ICT, board and system functional test-does it work; ICT testers and test software; The view of Silicon foundries, ASIC designers, IC manufacturers, and test engineer; SCAN vs. bed-of-nails, nodal visibility, circuit performance, and silicon overhead. Test Strategy and Rapid Prototypes Achieving low ppm factory defects, eliminating the hidden factory, and achieving maximum payback for test dollars; Product vs. strategy: high/low volume, number of PWA types, and PWA complexity; JIT and ppm defects; Eliminating "no-payback" test; How to minimize time for bareboard, ICT, and functional test; How to correct the factory; SPC, JIT, and DFS and minimize cost. www.americomseminars.com REGISTRATION INFORMATION Send the below requested information to: E-mail: americomseminars@aol.com Fax: 775-883-2384 Phone: 1-800-650-3033 (outside US, 360-479-0949) Mail the form to Americom Seminars, Inc.; 2533 No. Carson Street, Suite 4213; Carson City NV 89706 Sign up on our web page: www.americomseminars.com Share this seminar with colleagues who would benefit INFORMATION WE NEED 1. Session you wish to attend: -- Check our web page for the latest public seminars www.americomseminars.com -- or, Write down suggested dates for a seminar for your company 2. Name 3. Job Title 4. Company/Organization 5. Address 6. City, State, Zip 7. Work Phone (with area code) 8. Fax No. (with area code) 9. E-mail address 10. HOW DO YOU WISH TO PAY? --You can pay with credit card on our secure web site at: www.americomseminars.com --You can pay by check or money order or purchase order as well. SEE OUR WEB PAGE FOR FEES. www.americomseminars.com The three-day fee includes the following for each student: Two full days of instruction covering Test Comprehensive course notes Certificate of Completion indicating your participation in the course The six-day fee also includes Two additional days of instruction covering SMT Manufacturing Additional comprehensive course notes. Students at public seminars also receive Continental breakfast, lunch, and refreshments daily Firms that send three or more attendees to public seminars receive a $75 discount per person for 3-day seminars; $150 per person for 6-day seminars. PAYMENT · Checks or Money Orders made to Americom Seminars, Inc. · VISA, MasterCard, American Express, Discover · Purchase Orders; 10% fee for P.O.'s, waived if paid within 30 days of the invoice date. CANCELLATIONS You may cancel your enrollment up to 15 days prior to the seminar, but you must pay a $100 processing fee. Cancellations 2 to 14 days before the seminar pay a $250 fee ($150 for 1 day class). Cancellations the day before or day of the seminar, owe the full amount. You may substitute enrollees at any time. If this course is not held for any reason, Americom Seminars, Inc.'s liability is limited to refund of the full course fee. Questions: Email us at americomseminars@aol.com Call us at 1-800-650-3033 (outside U.S., call 360-479-0949) Write us at: Americom Seminars; 2533 North Carson Street Suite 4213; Carson City NV 89706 Lodging Options See our web page for this information. www.americomseminars.com Note: Lodging is not included in course fee. Questions: Email us at americomseminars@aol.com Call us at 1-800-650-3033 (outside U.S., call 360-479-0949) Write us at: Americom Seminars, Inc.; 2533 North Carson Street Suite 4213; Carson City NV 89706 Contact us about a private seminar at your location! You can register at www.americomseminars.com