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Robert Hanson, M.S.E.E.,
President, Americom Seminars, Internationally
Recognized Expert with over 35 years of experience. Americom Seminars has provided outstanding
electrical engineering seminars for over 16 years! Mr.
Hanson teaches a variety of courses. Brochure to e-mail to colleagues Return to main page |
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Choose
the seminar you are interested in for more information. Mr.
Hanson will present to your company on your schedule. One person, several
people, many people can attend; Mr. Hanson can present on ANY day of the week
and can present during the mornings, afternoons, and evenings. TEST SEMINARS The
importance of concurrent design approaches in Testing Surface Mount
Technology (SMT) becomes increasingly important as design complexity,
shrinking package size, higher quality requirements, and global competition
challenge all areas of electronic manufacturing. "Over the
wall" engineering approaches often result in costly delays in
production, untestable designs, and field
reliability problems. Getting new products to market faster ultimately
requires designs that are easier to produce, test, and service. This
course defines methods used by successful manufacturing companies to achieve
rapid prototypes, efficient design/manufacturing/test integration and
minimizing factory costs and Just-In-Time (JIT). TOPICS COVERED INCLUDE · Board size and parts
placement versus probing capability, large components and nail accuracy
solutions, test pad area for 6 sigma accuracy, blind and buried vias. · CAD drill tapes,
top/bottom side registration issues, tooling holes accuracy requirements,
test probes, daughter boards, clam shell fixtures, test top modules, the
lattice probe structure. · In-Circuit backdriving, wireless fixtures, PCB stress, probe guides,
ESD, no-clean bed-of-nails contamination issues. · Vision Testing - AOI,
laser, X-ray, laminography – what faults can it
detect. · Flying Probes – (FP) –
Accuracy, speed, FP versus ICT, FP versus SCAN, dual FP and ICT · Vectorless – Reverse diode bias,
inductive, capacitive. Test time and software savings, vectorless as an assistant for ESS. · Manufacturing Defects –
Types, causes and best detection method (bed-of-nails or vision) Got questions about a seminar at your location? Info about having a seminar at your site! Email us at americomseminars@aol.com Benefits of attending the Test Seminar This course
will benefit you As the trend toward increased
PCB complexity continues, there is a growing need to address testing issues
at increasingly earlier stages of the design process. With high-density boards comes the
challenge of 1GHZ device speeds and reduced physical access for testing,
fault diagnosis and repair.
Manufacturing high-quality reliable products requires concentrated
effort in two closely related areas:
Throughout this
three-day workshop, attendees will benefit from the instructor's extensive
"real-world" experience as a test engineer and technical
consultant. The format is designed to
provide a number of excellent opportunities for students to seek answers to
their unique SMT testing questions. Objectives: ·
To show how PC board design choices affect test strategy implementation ·
To demonstrate proven concurrent engineering approaches to PC board design
and layout issues that cut overall testing costs ·
To provide test-based tools to identify the causes of manufacturing defects
in SMT assemblies What You Will Learn: ·
How to test bareboards with blind and buried vias and controlled impedance requirements. ·
What causes PCB contamination dendrites and how to test for it? ·
How to define In-Circuit Test requirements at schematic capture and PCB layout
that insure adequate fault isolation and reduced functional test cost. ·
How to implement an overall test strategy to test early - test for less cost
and minimize the need for functional test. ·
Ability to recognize deficiencies in both schematic capture and PCB layout
that, when corrected, will greatly enhance the testability of your designs. ·
Awareness of the concerns of SMT Testing. ·
Bed-of-nails techniques for interfacing with very small pads and vias. ·
Best method of detecting manufacturing defects using either bed-of-nails,
vision, or flying probe. ·
An introduction to vectorless testing used to
detect shorts, opens, and other types of defects on high pin out areas of
PCBs. Who Should Attend: This seminar is designed
for engineers and their managers involved in the manufacture of SMT and mixed
technology electronic assemblies. It
will be beneficial to engineering personnel responsible for:
Got questions about a seminar at your location? Info about having a seminar at your site! Email us at americomseminars@aol.com Test Course Outline This course is for anyone who wishes to enhance their understanding of Test. Course Outline Schematic Capture Test Issues Board-level guides: initialization,
signal monitoring, feedback, oscillator control, and ambiguity groups;
LSI/VLSI test guides: partitioning and bus visibility, software/hardware
control, controlling microprocessors, three-state buses, memory elements,
synchronization, and clock control—examples of controlling CPU architectures
for in-circuit test; mechanical testability guides: accessibility, board
layout and board orientation, standard grids, design for simplicity/assembly/manufacturabilty;
Analog and hybrid guides: signal interfacing, analog test points and
partitioning analog circuitry; Scoring testability: three methods for scoring
design testability and identifying areas of untestable
designs. Routing Board
Layout Design Issues
Board size, parts
placement, large components, test pads, vias,
standard cells, auto drill/probe, and wire wrap issues; Spacing, skewing
error sources, actual pad size, chip shooters, vision systems, coplanarity; CAD drill tapes, top/bottom side
registration issues, tooling holes accuracy requirements, test probes,
daughter boards, clam shell fixtures, test top modules, the lattice probe
structure. Bareboard Test Issues
Effect of discrete
components, SMT, and both buried and distributive capacitance on EMI, stripline and impedance controlled boards, and curved
traces; Testing blind and buried vias; Bareboard test issues for high-density routing:
resistance, frequency, and signal quality; Today’s bareboard
test capabilities: megohm level, safety features,
speed fixturing enhancements and programming;
Automation techniques for transferring router (data set) files directly to
the B/B tester (i.e., eliminating software coding); Flying probe testing and
the concept of rapid prototypes (i.e., testing just-in-time). Student Participation: A variety of boards will be displayed to
illustrate concerns of testing bareboards. Also, videos will be presented showing
methods of performing clam shell and flying probe bareboard
test. In-Circuit Issues Standard cells and the
ability to via electrical nodes: No-clean solder paste and ICT bed-of-nails
(BON) contamination, vias under components—pros and
cons; Purpose of 100% nodal visibility to the bottom of the board; Design
rule checker requirements; Testing ASICs and MCMs; Board stress: what it is and how to eliminate it;
test pad size: fixture tolerances, pin tolerances, and error sources in the
B/B; Standard guides for automatic BONs fixturing; Why test spares; Detection of the fault cause:
solder, components, printing, chip shooting, cleaning, and the human
element-ICT must detect the fault, isolate the fault, and define the fault
cause; Backdriving: requirements for CPU bus
architectures, ASICs, and active components; What
to do when the IC model is not in the library; Why intelligent ICT is the
best SPC tool in the factory; What’s new in wireless fixtures, magnetic
plate, capacitive plate and reverse diode testing—how they work and what they
can do for your company’s ICT test capability; Can a board level functional
test be completely eliminated; industry examples. Student
Participation: A variety of populated
PCBs and videos will be used to reflect the concerns of testing PCBs with
today’s high-density requirements. Board Contamination What causes it and what are the effects in
electrical degradation, moisture absorption, and corrosive ionics; Surface insulation resistance: how to test it,
defining acceptable limits; Ionograph testing,
copper mirror test, solder mask corrosion test, and solderablity
test: what they are and when they should be used. Vision Types: Microscope, X-ray,
laser, AOI and laminography. What can they test, where should they be
used and how they can affect ppm defects.
Flying Probe (FP) Speed, accuracy,
capabilities, testing BGA, CSP, TAB, FC, and COB using FP. Emerging Technology
packages, videos and X8 magnifiers will be used to illustrate the need for
Vision and Flying Probe. IEEE 1149.1
Boundary SCAN
Why boundary SCAN: the
ever-increasing electrical node—I/O pin visibility ratio and increasing lack
of coverage using bed of nails; Understanding the spec: TAP control, data
instruction registers, the five test instruction, running BIST; SCAN for ICT,
board and system functional test—does it work; ICT testers and test software;
The view of Silicon foundries, ASIC designers, IC manufacturers, and test
engineer; SCAN vs. bed-of-nails, nodal visibility, circuit performance, and
silicon overhead. Test Strategy
and Rapid Prototypes
Achieving low ppm factory defects, eliminating the hidden factory, and
achieving maximum payback for test dollars; Product vs. strategy: high/low
volume, number of PWA types, and PWA complexity; JIT and ppm
defects; Eliminating “no-payback” test; How to minimize time for bareboard, ICT, and functional test; How to correct the
factory; SPC, JIT, and DFS and minimize cost. Got questions about a seminar at your location? Info about having a seminar at your site! Email us at americomseminars@aol.com
Comments
about the web pages, contact Jim Hanson at hansonjb@gmail.com
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about the web pages, contact Jim Hanson at hansonjb@gmail.com |