Robert Hanson, M.S.E.E., President, Americom Seminars, Internationally Recognized Expert with over 35 years of experience. Americom Seminars has provided outstanding electrical engineering seminars for over 22 years! Mr. Hanson teaches a variety of courses. Choose from any of Robert Hanson's renowned high technology seminars. Each is carefully designed to meet your needs and Mr. Hanson comes to your location. Return to main page www.americomseminars.com

Mr. Hanson will present to your company on your schedule. One person, several people, many people can attend; Mr. Hanson can present on ANY day of the week and can present during the mornings, afternoons, and evenings.

ENHANCING RELIABILITY SEMINARS Got questions about a seminar at your location? Info about having a seminar at your site! Email us at americomseminars@aol.com ENHANCING RELIABILITY COURSE (2-day) Intelligent Testing, Parts Selection/Placement, PCB Layout, and Lead/Lead-Free Assembly Issues WHY THIS TUTORIAL Reliability is much more than performing analysis using MIL-HDBK-217 or calculating Failure Modes and Effects Analysis. It is well known that IC manufacturers over the years have improved the reliability of their merchant chips to levels where they usually fail, not due to their quality, but due to application misuse. This tutorial will focus on the main issues of reliability today which consist of (a) disciplines of designing the bareboard, (b) component selection and placement, (c) controlling the production line for minimum ppm defects, (d) issues of lead-free assembly (like tin whiskers), (e) testing for fault detection/fault isolation and correcting the processes, and (f) intelligent ESS using HALT/HASS for eliminating infant mortality. WHO SHOULD ATTEND Electrical engineer circuit designers, PCB design engineers, manufacturing engineers, test engineers, production personnel, Reliability engineers, and anyone interested in the design, production, and testing of LRUs and SRUs. COURSE OUTLINE 1. Building Reliability in the Printed Circuit Board (PCB) It is a well-known fact that a company’s high-speed, high-edge rate product is highly predicated upon the design of the bareboard. If it is not designed properly, it can experience some or all of the following problems: a. Transmission line resonance b. Ground bounce c. Crosstalk d. Lack of bypassing capability e. Power delivery f. Both conducted/radiated failures Therefore, if these issues are not eliminated at design conception, then what is the effect on reliability? Geometry, C, L, Zo, Interrelationships Infinite Uniform Transmission Line Effects of Source and Load Impedance Special Transmission Line Cases Reliability issues of receiver ESD diodes due to design flaws in layout out the transmission line (metal migration, ionic creep, dendrite growth). How to stack Printed Circuit Board (PCB) layers (e.g. 4 and 6 layer) for Zo and crosstalk control, Cu fills on signal layers, minimizing warpage, CTE mismatch, solder shear and stress, and via cracking Testing blind and buried vias: Bareboard test issues for high-density routing: resistance, frequency, programming Board Design and Layout Guidelines for Reliability Routing PCB Density Protective Coatings Solder Masks Issues of PCB Design and Layout for High-Density Pinout Configurations PCB Layers Vias Signal Quality PCB Material PCB Material Characteristics 2. Parts Selection and Intelligent Parts Positioning If the parts selection (mainly packaging) and parts layout are not properly addressed at design conception, then some or all of the following problems could occur: Bridging Shorting Skewing, tombstoning, and missing components CTE mismatch - solder shear, and stress Overheating And many of the problems listed in 1 above Therefore, if these issues are not addressed at design conception, what is the effect on reliability? Electronic Packages: QFPs, PGAs, SOIC, PLCC, BGA, COB, TAB, FC, CSP Separating analog from ECL/PECL, and TTL/CMOS the concept of moats/floats/drawbridge Split planes - CMOS/TTL, PECL, and analog using the same bias voltages Design strategies at North Grumman-Rolling Meadows for protecting sensitive analog from noisy digital Partitioning and bus visibility, software/hardware control, controlling microprocessors, three-state buses, memory elements, synchronization, and clock control - examples of controlling CPU architectures for in-circuit test to enhance FD/FI on the production line. Conventional Packages Rs, Cs, Diodes, beads, and inductors SMT Components Thermal shock and joint failures Packaging methods Integrated Circuit Trends IC Density, IC Chip Size, IC Feature Size IC Performance, IC Operating Voltage Flip Chip, DCA, C4, COB, Micro BGA, CSP ASICs and MCMs Emerging Packages: BGAs CBGA Packages PCB Assembly of CBGAs PBGA Packages PCB Assembly of PBGAs Popcorn effects and solutions of BGAs Advantages and disadvantages of BGAs Mounting SMT and NSMD pads, vias in pads versus vias on stringers 3. The Production Line and Issues of Lead/Lead Free The items listed below will be discussed from both the leaded and lead-free (LF) prospective. Along with the instructor’s class notes, the full course notes of Dr. Ron Laskey’s LF tutorial will be on display for reference. Probably the most reference case of LF incompatibility is the aborted Galaxy Space shot where a $50 million dollar program was wiped out by Tin Whiskers. Soldering Reflow soldering Basic Steps in Soldering Soldering Problems Wave Soldering Soldering Methods Factor Influencing Poor Quality Soldering Cleaning Types of Solder, Contamination, Cleaning Chemistries, Cleaning, Cost Studies, Contamination Cleaning Issues of Advanced Packages Issues of Cleaning under small standoff packages Can contamination be removed from under small standoff packages? What about SIR and fidelity at high frequency? What about dendrite growth due to fine line trace spacing? 4. Testing for Reliability As Test overseer at Boeing Commercial Avionics, the instructor can cite case after case where intelligent testing enhanced the electrical card reliability of not only commercial avionics, but also military avionics. Therefore, IMO performing the correct test at the correct level is the best way of enhancing reliability. No-clean solder paste and ICT bed-of-nails (BON) contamination, vias under components--pros and cons; Purpose of 100% nodal visibility to the bottom of the board. Why test spares; Detection of the fault cause: solder, components, printing, chip shooting, cleaning, and the human element-ICT must detect the fault, isolate the fault, and then define the fault cause. Why intelligent ICT is the best SPC tool in the factory; What’s new in in wireless fixtures, magnetic plate, capacitive plate and reverse diode testing--how they work and what they can do for your company’s ICT test capability Bead Probe Technology:- The new concept for providing 100% fault detection/fault isolation for high-density PCBs Board Contamination: What causes it and what are the effects in electrical degradation, moisture absorption, and corrosive ionics: surface insulation resistance: how to test it, defining acceptable limits; Ionograph testing, copper mirror test, solder mask corrosion test, and solderability tests: what they are and when they should be used Vision: Types: Microscope, X-ray, laser, AOI and laminography. What can they test, where should they be used, and how they can affect ppm defects. Fling Probe (FP): Speed, accuracy, capabilities, testing BGA, CSP, TAB, FC, and COB using FP 5. ESS-Finding Infant Mortality The HALT/HASS method What Dr. Greg Hobbs does not tell you and disciplines of the Morey Corporation and Boeing Commercial Avionics. NOTE: A number of videos (typically 5 minutes each) will be shown on manufacturing production line defects, testing strategies, soldering, and components. Got questions about a seminar at your location? Info about having a seminar at your site! Email us at americomseminars@aol.com Comments about the web pages, contact Jim Hanson at hansonjb@gmail.com www.americomseminars.com

Americom Seminars provides exceloin us at an Americom Seminar!

Comments about the web pages, contact Jim Hanson at hansonjb@gmail.com