The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have reached the 17ps rate. This has resulted in high-speed design problems, such as:

· A lack of control over impedance and reflections

· Crosstalk and bypassing failures

· Time delays, false triggering, and reflections

· Failure to meet EMI and FCC requirements

It is the edge rate, not the frequency, that exacerbates this problem, so even if your design is for moderate frequency, the edge rates can cause these designs to reflect the high-speed effects.

Most designs today use a microprocessor and today’s micros have clock rates over 1000 times higher than the original 8- and 16-bit machines. A key factor is the minimization of the semiconductor device (now at 32 nm) leading to less parasitic L and C, and thereby faster switching rates. This phenomenon also is apparent in RAMs, ROMs, ASICs, and gate arrays. This leads to PCBs requiring terminators, new CAD routing disciplines, and component additions to minimize ground bounce effects. More and more designs are requiring these faster devices to meet more demanding specifications that match or beat the competition.

The following one-day courses comprise a week of instruction in high-speed digital design/EMI:

· Transmission Lines

· Crosstalk, Layer Stacking, Separating Analog/Digital Planes, and Terminations

· Bypassing, Power Delivery, Vias, Connectors, and Buses

· Differential Signaling and Clock Distribution Control

· Key Issues for EMI/EMC: How to Design and Build a Compliant System

These courses provide participants with the tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. Emphasis is placed on cost-competitive design without sacrificing high-speed integrity.

The courses are intended for digital design engineers, design managers, test engineers, EMI/EMC engineers, IC digital logic designers, project managers of high-speed designs, communication engineers, and military digital engineers. No advanced math is required, although participants will find it helpful to bring a scientific calculator to the course. The material is presented at a technical level that provides experienced designers with information to design and lay out a high-speed PCB that meets signal integrity (SI) and EMI.

Each course may be taken on a stand-alone basis or combined as needed. While each subsequent course builds upon the previous instruction, participants may enroll in any course or combination.

CADENCE DEMOS

Each day at the conclusion of the training session Cadence will demonstrate examples of the lecture material. This will provide the student with real world examples of the methods used to design it correctly. The following provides the itinerary of the demonstrations.

Here is the list of demos designated for each day's topic:

TRANSMISSION LINES (Day 1) - Fundamentals of transmission lines including stripline vs micro-strip.

Cadence Demo: Pre- and post-route SI analysis using ideal and lossy transmission lines.

CROSSTALK (Day 2) - Stack-up optimization and forward/reverse crosstalk.

Cadence Demo: Pre- and post-route crosstalk analysis as well as crosstalk estimation.

POWER DELIVERY (Day 3) - Proper use of decoupling capacitors and identifying power plane resonance.

Cadence Demo: Allegro PCB Power Delivery Network (PDN) analysis

DIFFERENTIAL SIGNALING (Day 4) - Loosely vs. tightly coupled differential pairs; clock distribution.

Cadence Demo: Tandem and broad-side differential pair routing and analysis.

EMI/EMC (Day 5) - Source, path, and receptor as well as how EMI/EMC tests are conducted.

Cadence Demo: EM control rule checking and EMI net analysis.

Mr. Hanson answers questions about the 5 One-Day Courses

1. MON. Transmission Lines

Course Program.

Fundamentals

· Frequency, time, and distance

· Lumped versus distributed systems

· EM fields

· Geometry, C, L, and Z_o interrelationships

· C&L resonance

High-Speed Properties of Logic Gates

· Quiescent versus active dissipation

· Driving capacitive loads

· Input power and external power

· TTL, CMOS, SiGe, In Ph, ECL, and GaAs; output power, speed and engineering disciplines, Dv, di effects and voltage margins

· Intersymbol Interference (ISI), eye diagrams and jitter

· Shoot Through Current (SSO) and how to minimize it

· Ground bounce, lead inductance, Simultaneous Switching Noise (SSN)

· Viewing a serial data transmission system, the eye pattern closure: ISI, skin effect, and tan loss

· PLL and DLLs

Transmission Line Characteristics

· The quality factor, Q, and why lumped circuits can ring and cause EMI

· Infinite uniform transmission line

· Effects of source and load impedance

· Special transmission line cases

· Determining line impedance and propagation delay using TDR and VNA

· Skin/proximity effect and dielectric loss

· The capacitive load: Z_o and propagation delay

· Matching Z_o with trace alturations (neckdowns): minimizing the C load

· 90^o, 45^o bends: are they concerns?

· Characteristics of T. lines: coax, pair, micro strip, buried micro strip, stripline and differential: asymmetric, dual, edge

2. TUES. Crosstalk, Layer Stacking, Separating Analog/Digital Planes, and Terminations

Course Program

Ground Planes and Layer Stacking

· High-speed current follows the path of least inductance

· Crosstalk in solid and slotted ground planes

· Inductive/capacitive ratios for micro strips, striplines, and asymmetric, dual, and edge differentials

· Guard traces: do they. stop crosstalk, can they resonate?

· Near-end and far-end crosstalk

· Separating analog from ECL/PECL and TTL/CMOS the concept of moats/floats/drawbridge

· Split planes: CMOS/TTL, PECL, and analog using the same bias voltages

· How to stack printed circuit board layers (e.g., 4, 6, and 10 layer) for Z_o and crosstalk control, Cu fills on signal layers, minimizing warpage

· Interplane capacitance: how thin, what material and stackup placement?

· SIR vs. frequency, software for performing crosstalk and ground bounce tests

Terminations

· End/source/middle terminators

· AC biasing for end terminators, where should it be used and how to choose the capacitor

· Hairball networks, bifurcated lines, and capactive stubs

· Terminating differentials: eliminating common mode and minimizing power

· What causes differentials unbalance?

· Diode and active terminators, resistor selection, and crosstalk in terminators

3. WED. Bypassing, Power Delivery, Vias, Connectors, and Buses

Course Program

Power Systems

· Providing a stable voltage reference: Cu planes

· Distributing uniform voltage: sense lines, bulk C, and interplane C

· Choosing a bypass capacitor: electrolytic/tantalum and ceramic

· Power plane resonance: serial and parallel, how to minimize both

· Designing a .1 ohm bypass system up to Fknee

· Designing for constant ESR

· IC die capacitance, discrete C in the IC package

· Why the 0201: both for better bypassing and EMI control

· Minimizing L-capacitor layouts for SOICs, PLCCs, and various configurations of BGAs

· Layout requirements for power delivery

Vias

· Mechanical properties of vias

· Capacitance and inductance of vias

· Return current and its relation to vias

· Through hole, blind, buried, micro vias

· Intelligent vias and autorouters

· Via discontinuity and via resonance concerns

Connectors and Cables.

· Mutual and series inductance: how connectors create crosstalk
and EMI

· Using connectors on a multidrop bus (Z mismatch reflection) and how to match Z_c to Z_o

· Measuring coupling in a connector

· Continuity of Gnd underneath a connector

· Special connectors for high-speed requirements: crosstalk and matching Z_o

· Matching signaling through a connector (impedance discontinuity)

Buses

· Multidrop systems: drivers, transceivers, and designing a high-speed bus

· How they function, clock rates, typical failures

· ISI: minimize the effect with equalization and preemphasis

· LVDS: types, unbalance, noise, layout, and making them function

· Methods to speed up busses: distributive driving and load capacitance matching

4. THURS. Differential Signaling and Clock Distribution Control

Course Program

Differential Signaling

· Attributes/drawbacks of loosely/tightly coupled differential pairs

· Definition and examples of differential and common mode V and I

· Differential impedance: odd and even modes

· Advantages and disadvantages of edge (side by side), broadside (dual), asymmetric, and microstrip differentials

· Reflections and crosstalk in differentials; metastability, Clk skew, driver skew, bit pattern sensitivity, ISI, skin effect, and dielectric constant; jitter, BER, and the eye diagram

· Matching electrical lengths

Clock Distribution

· Timing margin and clock skew

· Using low-impedance drivers and clock distribution lines

· Source termination of multiple clock lines

· Controlling crosstalk on clock lines

· Delay adjustments: serpentine traces/DACs and varactors for dynamic delay

· Differential distribution

· Controlling clock signal duty cycle using the integrator

· Source synchronous clocking, DDR and RDRAM

High-Speed Clocking

· Clock skew and jitter

· PLLs, DDLs, serpentine traces, and programmable delays

· Source and end termination considerations for star, daisy chain, and driving multiple loads

· Pre-emphasis and equalization techniques

· The effects of ISI, skin, and dielectric losses

· The effect of various base materials of long-haul transmission; the effects of eye closure on BER

· A real-world example of compensation techniques

5. FRI. Key Issues for EMI/EMC: How to Design and Build a Compliant System

If you are a design engineer, it pays to know how and why EMI testing is conducted, as well as the typical causes of failure. This course provides ways to prevent common EMI/EMC problems regarding power supplies, cables, connectors, slots, discontinuity of ground planes, and more. The focus is on EMI and RFI issues regarding PCBs as well as relevant EMI regulations in the U.S. and the European Union. Highlights include PCB radiation basics, radiation and bypass on PCBs, PCB radiation suppression techniques, grounding designs/filtering, crosstalk/termination, power and ground planes, antenna loops, spread spectrum clocking, and differential-mode and common-mode radiation.

This course covers the following topics: how the EMI/EMC tests are conducted and how to avoid many configuration layout problems; design techniques to minimize radiation/susceptibility for both digital and analog PCBs; grounding and shielding techniques; and how to overcome radiation problems with connectors, cables, and hardware slots.

Course Program

EMI, Source, Path, and Receptor

· Why all three must be present to have an EMI problem

· EMI regulations/standards for USA, Europe (EU), and Asia

· Course notes provide a detailed description of all the test requirements, equipment to conduct the tests, and the governing bodies/committees that mandate the tests

Threats

· RFI

· ESD

· Power Disturbances

· Internal

EMI Issues

· Frequency

· Amplitude

· Time

· Impedance dimensions

EMI Regulations

· Commercial

· Military

· Avionics

· Automotive

· Medical

· Communications

Conducting an EMI Test

· Precompliance, compliance testing, and post-audit testing

· What is uncertainty and how does it affect the test plan?

How Tests are Conducted

For all of the following tests, the hardware instrumentation, layout, pass/fail criteria, and tips/techniques to pass the test are covered. The test site also is defined, i.e., OATS, screen room, anechoic chamber, and TEM cell. The step-by-step sequence of how each test is conducted is detailed.

· Conducted emissions

· Radiated emissions

· RF immunity

· Conducted RF immunity

· ESD

· Lightening

· Electrical fast transient

· Interference Coupling Mechanism - What is the near/far field, coupling modes, resonance and why are parts placement, proper terminations and grounding so important.

· Grounding designs/Filtering – Single ground, modified and multipoint grounding, which one should be used for your design.

· CM Radiation – Why is common mode (CM) the major problem versus differential mode (DM)?

· Antenna Loops – Why are antenna loops the major cause of radiated emission failures for PCBs?

· Basics of PCB Radiation – Why do both lumped and distributive (transmission lines [T.L.]) circuits radiate? Why does a high Q circuit radiate? How do you terminate a T.L. to minimize radiation? What about the capacitive load and why does it cause radiation?

· PCB Suppression Techniques – Terminations, filters, and devices – how are they used to suppress radiation?

· Switching Mode Power Supplies (SMPS) – SMPS Chopping Frequency.

· Why is it the major cause of conducted emissions?

· Filters – Schematic configurations of harmonic filters.

· What happens when transients/ESD hits the SMPS mains?

· What are the immunity concerns?

· What are screens and snubbers, and how it a transformer wound?

· Crosstalk – Inductive/capacitive, forward/backward – How does it occur? Why does it cause radiation and how is it minimized?

· How to minimize PCB antenna loops. Do vias cause radiation?

· Power/Ground Planes – Splits, slots, moats, floats, drawbridge, how to design for minimizing emissions from power/ground planes. How to design for digital/analog (multibias) and single bias PCBs.

· Picket fences, the 20H rule and Cu fills – What can they do to suppress emissions?

· Ideal stackups to be EMC.

· Spread Spectrum Clocking – Why does it suppress radiated emissions? Under what conditions can it be used? Is there a better method?

· Bypass and Radiation on PCBs – Why use the 0201, Ycap and four terminal cap? Types of innerplane capacitance and does innerplane capacitance help with emissions?

· Interference Coupling Modes – Why does ground bounce cause differential and common mode noise and how does that cause emissions?

· Near/Far Field - What determines the breakpoint between them and what happens to the characteristic impedance at the breakpoint?

· Differential/common coupling modes and resonance – What are the quarter length resonant mode differences when the load impedance is very high versus very low?

· Analog circuitry – Transients, filtering, grounding and noise isolation. Opto couplers versus spin resistors; which is better?

Cables/Connectors Interfaces, Filtering and Shielding

· Capacitive and Magnetic Shielding – What is the difference and how should the shield be tied to ground for either case?

· Slots – Why do they radiate and is the radiation through them predictable?

· Shield Grounding – How should shields be tied to ground to minimize circulation current?

· Cable Radiation – Radiation through the shield and at the connector bulkhead connection.

· Shielding Types – When do we use Cu and Al versus mu metal, steel, or permalloy?

· Transfer Impedance – What is it? Why is it detrimental to shielding, and how is it minimized?

· Shielding Connection – Leakage – How to design a non-emission connection of a connector to a bulkhead.

· Loss of Ground Plane in Cables – Why does it cause crosstalk, radiation, reflections and propagation delay?

· Cables Configuration – What shielding/grounding techniques should be used to minimize crosstalk and radiation?

· Antenna Loops with Cable Connections – Why do shielding pigtails cause emission non-compliance?

· High-Speed Connectors – How are they configured to minimizie skin effect, dielectric loss, crosstalk, and radiation?

· Filtering – Types of filters, their attenuation capability and how should they be mounted?

· Shielding vs Filtering – Cost tradeoffs versus attenuation capability –When should either or be used?

· Using Ferrites – Amperes Rule - Why do they work so well for both DM and CM?

· Filtering Mains Supply – Using capacitors, chokes, and torroids. Filtering both DM and CM noise.

· Using Transients Suppressors on Mains and I/O lines – Where should TVSSs, Spark Gaps, Varistors and Zeners be used.

· Radiation Through Shields – Current density versus skin depth, incident versus reflected fields

Register for the Cadence Seminars

Pay for your Cadence Seminar

Brief biography: Robert Hanson

Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: dad

Robert Hanson, MSEE has unmatched experience in teaching and knowledge of electronics. As a Testability Overseer for Boeing Commercial Airline products, Mr. Hanson has worked with non-EEs and EE’s. He understands the need to use clear communication and he spends extra time answering student questions during his presentations or privately afterward.

Mr. Hanson has over 40 years of experience in the design manufacturing and testing areas. His initial education was in (BSIE) and Business Administration (BSBA). After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and LoraL, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implementing robotics, and participating in producibility studies and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field, commercial and military as the testability overseer for Boeing Commercial Airline products.

Building on that practical knowledge, Mr. Hanson has taught these courses many times receiving outstanding reviews each time from participants. He has presented his courses for the University of California at Berkeley, University of Wisconsin, University of Oxford (England), Seattle Pacific University, University of Washington, and most recently he teaches several classes for University of California- Los Angeles as well as for over 100 private companies on-site.

His clear instruction builds on 40 years of working experience in electronics including in manufacturing, hardware testing, and operational/test software. His teaching also reflects the fact that he has taught electronics courses throughout the United States, Europe, South Africa, the Middle East, and Asia.

Mr. Hanson has an M.S.E.E. from the University of Southern California, a B.S.E.E. from the University of Washington, and a B.S.I.E. and a B.S.B.A. from the University of North Dakota. He brings his practical experience and educational background to present a seminar that both EEs and non-EEs will find accessible and useful.

AWARDS: Boeing Company Aerospace Man of the Year for saving $6,000,000 for inventing a new testing technique for the Boeing B-1 bomber electronics.

Robert Hanson has done private seminars for 3-Com, Advanced Fibre Communications, Alcatel, Allied Signal, AMD, AMD-Dresden, Apple, AT&T, Autoliv, Boeing, Chrysler, Cisco, Compaq, Cray, da Vinci Systems, Data Device, Dell, Delphi, EDA Technologies-So. Africa, Ford, Freescale Technologies, Gateway, GE, Gen Rad, Honeywell, HP, IBM, Intel, Kaneta High Tech Materials, KLA Tencor, Lockheed, Lucent, LXE, Marconi, Micron, Motorola, NASA, NEC, eLuminant, Navico, Nortel, Northrop Grumman, Panasonic, Qualcomm, Raytheon, Rockwell, Samsung-Korea, Solectron, Storage Tek, Sun, Tektronix, Teradyne, TI, TRW, Tyco Electronics, Tycom Laboratories, U.S. Trade Commission, United Defense, Wilson-Sonsini-Goodrich and Roseti Law Firm, Xerox, and Xilinx.

AND

ABT Media – Singapore, Autoliv, Advanced Electronic Diagnosis (AED) Saudi Arabia, Atkins Tehcnical, Inc., Bacharach, Inc., BBN Graphics, Benthos, Bourns, Compression Labs, Inc., Coulter, Dalphax, Dynalco, NASA-Edwards AFB, Hewlett Packard - Barcelona, Eldec, First Inertial Switch, Fluke, Genicom, Hathaway, Johnson & Johnson, Jet Propulsion Labs (JPL), Loral Aerospace, Martin Marietta, McBeth, Medrad, Medtronic, Motion Engineering, Inc., Norsat International, Okidata, Pharmacia Deltec, Precor, Satcom, Southern Research Institute, Wellex, Jefferson Labs, Aselsan (Turkey), Schmitt, NVE, Mc Dermott, Will, and Emery Law Firm, FLIR, Data I/O, Pulsecom, Symbol Technologies, U.S. Navy - Idaho, and JSI.

Fees

$695 for the first day selected.

$645 for the second day selected.

$595 for the third day selected.

$545 for the fourth day selected.

$500 for the fifth day selected.

Days selected do not have to be sequential.

10% discount for each day that 2 from same company attend.

15% discount for each day that 3 or more from same company attend.

Example: Attendee A takes 3 days of classes (not necessarily sequential). $695 for Day 1: $645 for Day 2: $595 for day 3 for a total of $1935.00. Should 2 come from same company there is an additional 10% discount for each attendee, or a savings of $193.50 per attendee for all three days. 15% discount if 3 or more attend from same company.

For courses "Transmission Lines;" "Crosstalk, Layer Stacking, Separating Analog/Digital Planes, and Terminations;" "Bypassing, Power Delivery, Vias, Connectors, and Buses;" and "Differential Signaling and Clock Distribution Control," you will receive one copy of the Johnson/Graham text book, "High-Speed Digital Design: A Handbook of Black Magic." For course "Key Issues of EMI/EMC: How to Build a Compliant System," you will receive one copy of the Tim Williams book, "EMC for Product Designers (4th Edition)." You will also receive a supplemental text for each day's topic.

If you already have the text, we will reduce your tuition by the cost of the book. Let us know when you register.

Lunch and snacks will be included in the fee as well.

American Express, Visa, Mastercard are accepted. Please note that the statements will read "Haji, Inc." not Americom Seminars, Inc. or Cadence. You can also send checks or money orders (no cash) made out to "Americom Seminars, Inc." and mail to Americom Seminars, Inc., c/o Robert Hanson, P.O. Box 4220, Bremerton WA 98312. Please include registration form if mailing.

We will verify the correct amounts for fees with you before processing to insure all discounts are included. We will confirm your registration upon receipt.

Register for the Cadence Seminars

Pay for your Cadence Seminar