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Mr. Robert Hanson is ready to instruct and consult. High Speed Digital
Design, EMI/EMC, Essentials of Electronics, SMT Manufacturing, BGA, Enhancing
Reliability, Test Cadence HSDD & EMC-EMI Seminars Mr. Hanson answers questions about design and his
seminar. --What are the most significant problems
you are seeing in high-speed digital PCB designs these days? It's dependent on the design,
i.e. high speed/low speed, high edge rate/lower edge rate and also simple PCB
or large backplane design. However, some of the glaring problems are
transmission line reflection due to the capacitive load, ground bounce,
crosstalk between violent aggressors (like CMOS) and sensitive victims (like
ECL/PECL and analog), bypassing & power delivery, common mode
differential pair problems and high speed clock loading. --How fast are the fastest boards you are
seeing? How many components and pins, and what form factors? Several students in my classes
are designing backplane, servers and blades that have clock frequencies
up 11GHz. I consulted for a company that built a backplane with 65 BGAs
having over 600 balls each, 34 layers and over 58K solder
joints. The fastest digital board (not microwave) was an aerospace design
running at 43 GHz. Regarding components, there is a BGA graphics
processor with a clock speed of 5.6GHz and has over 3400 balls. How
would like to reflow solder that one? --Day 1 of your seminar covers
transmission lines. What are the most important points you’ll be making? Most significant would be
defining the cutoff conditions to determine when a land trace acts
like a transmission line vs a lumped
circuit. This will determine to a large degree the termination scheme
that will be used to minimize reflection. Also of importance would be
to define skin effect, dielectric loss and proximity effect. The
interesting point about proximity effect is that if the spaces are just a
fraction of the land width (like 5 to 1) this will create more signal
loss than skin effect, dielectric and surface roughness
combined. Another subject is signal delay for microstrip and stripline.
With microstrip the delay is not the same for bare,
solder mask (SM) covered and conformal covering, i.e.
encapsulation over the SM. Also, providing the analysis for all the
characteristic impedance and delay expressions for microstrips,
buried microstrips, striplines
and differentials will be included. --What design techniques are needed to
keep signal integrity under control? Excellent communication among
the EE Design engineer, the PCB design engineer, the test engineer and
manufacturing engineer is critical. Also, close coordination with
the bareboard vendor and the EMS supplier are
essential. The inputs from all of these will have an effect as to the
best design techniques for achieving signal integrity. A very high
priority is to conduct digital simulation ( like Cadence Allegro SI) and
EMI/EMC simulation like CST, i.e. the more up front potential problem
identification the less debug time, less problems during compliance testing
and quicker time to market. --What crosstalk problems are you seeing
in high-speed designs (Day 2)? The ever increasing high
density board layouts is very challenging. I
have seen designs where 2s and 2s are being used due to density/packaging
restrictions. Interference between CMOS/TTL high edge rates and
ECL/PECL is another situation. A major concern is the sensitive analog
in close proximity to the fast edge rate digital signals. This is where
guard traces around the analog traces become effective. --How does crosstalk impact layer
stacking? To control crosstalk there has
to be a distance between the aggressor and the victim versus the distance to
the reference ground plane (or power plane). Therefore, the trade off
in many cases is how do I minimize my stackup
layers (cost consideration) versus controlling the crosstalk and also the
characteristic impedance which is also a correlation between trace width and
distance to the reference plane (or planes as in striplines).
As each new design is released there is typically a higher clock rate with
higher edge rates, more signals per IC package and a need for higher density
which exacerbates crosstalk. In my estimation this will be one of the
major challenges for the design community as competition and cost
considerations will highly influence the layer stacking. --What do designers need to do to ensure
adequate power delivery within a specified power envelope (Day 3)? In one word it's
inductance. How much inductance is inherent in the mounted capacitor
loop and the ESL of the capacitor needs to be identified.
Also, the characteristics of the power and ground planes. Today
cores are being produced with less than 1 mil-in of dielectric
thickness. If these are used, they will they enhance the power
delivery but at what cost. Designers must know the bypassing
capability of their output drivers. The only way to overcome
SSO is at the die level. So the need is to provide the proper
dq/dt at the needed IC
pin at the right time. Therefore, one must know the maximum level of
power delivery noise allowed in the overall noise budget. With that
knowledge the strategy is to provide the correct IC die capacitance, innerplane capacitance, discrete capacitance and
capacitor types (X2Y, Y cap, reverse electrode, etc.) to achieve this
goal. Another factor, especially as frequency increases, is the
anti/parallel resonance considerations which may require breaking up the
capacitors into banks with different ESRs and different loop inductances. --What “best practices” do you advocate
for differential signaling and clock distribution (Day 4)? Probably the main concern is
differential unbalance caused by the two lines not being the same electrical
length. This causes common mode and is the main reason differentials
can fail EMI radiation. Another consideration is to assign the more
sensitive pairs as striplines. Avoid broadside
layouts, i.e. make them be edge to edge. Broadside in many cases can
render the design inoperable due to returning currents being contained on
different ground planes (or possibly power plane(s)) which can cause the
receiver to see a totally different noise spectrums on
its inputs. --When does EMI become a concern in PCB
design, and what do designers need to know (Day 5)? The two big concerns are
radiated emissions and ESD. All radiated emission formulas have both
edge rate and frequency as two of the parameters. Therefore, many of
the signal integrity rules also apply to EMI. The main cause of
radiation from circuit boards is the size of the antenna loop,
that is the pathway the current takes to the load and the
direction/pathway that it takes to return to the VRM. The more area
this entails, the more radiation. Regarding ESD, the designer must know
the ESD pulse edge rate which in turn will define the protection device
(TVSS) or the filter. Another
concern today is the ever increasing frequency, higher clock rates and power
dissipation in the design. Designs are becoming higher density with more power dissipation (P=F*C*Vsquared). Due to the higher clock rates the
apertures are decreasing in size to minimize harmonic radiation, i.e. the
wavelengths are becoming shorter. However, with smaller apertures the
design is much less efficient in allowing heat to escaping the
enclosure. This is one of the major concerns in EMI mechanical
compatibility design. --What Cadence tools will the seminar
demonstrate? Each day at the conclusion of
the training session Cadence will demonstrate examples of the lecture
material. This will provide the student with real world examples of the
methods used to design it correctly. The following provides the
itinerary of the demonstrations. Here is the list of demos
designated for each day's topic: TRANSMISSION
LINES (Day 1) - Fundamentals of transmission lines including stripline vs micro-strip. Cadence Demo:
Pre- and post-route SI analysis using ideal and lossy
transmission lines. CROSSTALK (Day
2) - Stack-up optimization and forward/reverse crosstalk. Cadence Demo:
Pre- and post-route crosstalk analysis as well as crosstalk estimation. POWER DELIVERY
(Day 3) - Proper use of decoupling capacitors and identifying power plane
resonance. Cadence Demo:
Allegro PCB Power Delivery Network (PDN) analysis DIFFERENTIAL
SIGNALING (Day 4) - Loosely vs. tightly coupled differential pairs;
clock distribution. Cadence Demo:
Tandem and broad-side differential pair routing and analysis. EMI/EMC (Day 5) - Source, path, and receptor as well as how
EMI/EMC tests are conducted. Cadence Demo: EM
control rule checking and EMI net analysis. --What’s your most important advice for
clients working with high-speed digital boards? One could write a book on this,
but to briefly state the advice: know the rules of high speed design, work as
a team in the prototype design, simulate the design, and work closely with
the bareboard vendor. Upcoming Seminars Mr. Hanson is doing Consulting Mr. Hanson can do for you Seminars Mr. Hanson can present at your Location Question? Contact us via Email: americomseminars@aol.com We want to hear from you. |
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Americom
Seminars has provided outstanding electrical engineering seminars for
over 25 years. Contact us via Email: americomseminars@aol.com Americom
Seminars, Inc. 375
N. Stephanie St. Suite
1411 Henderson
NV 89014-8909 Phone: 775-841-9432 |
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pages, contact Jim Hanson at hansonjb@gmail.com |
