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Robert Hanson,
M.S.E.E., President, Americom Seminars,
Internationally Recognized Expert with over 40 years of experience. Americom Seminars has provided
outstanding electrical engineering seminars for over 25 years! Mr. Hanson teaches a variety of courses. High Speed Brochure to
e-mail to colleagues High Speed Brochure for printing
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One Day
Seminars. Lean
and efficient. Good Timing. Mr. Hanson will present to your company on your schedule. One person, several people, many people can attend; Mr. Hanson
can present on ANY day of the week and can present during the mornings,
afternoons, and evenings. You can have a one day course; you can do up to
five days with the courses listed below. Customize to what you need. |
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Mr. Hanson travels to you
and notes and presentations can be tailored to your company for your products
and design needs. THE FIVE ONE-DAY COURSES OVERVIEW: The speed of today’s logic devices
mandates that the interconnects on PCBs must meet
the high switching rise/fall times of these devices. Switching edges are in
the 200ps to 300ps range and some devices have edges that have reached the
17ps rate. This has resulted in high-speed design problems, such as: ·
A
lack of control over impedance and reflections ·
Crosstalk
and bypassing failures ·
Time
delays, false triggering, and reflections ·
Failure
to meet EMI and FCC requirements It
is the edge rate, not the frequency that exacerbates this problem, so even if
your design is for moderate frequency, the edge rates can cause these designs
to reflect the high-speed effects. Most
designs today use a microprocessor and today’s micros have clock rates over
1000 times higher than the original 8- and 16-bit machines. A key factor is
the minimization of the semiconductor device (now at 32 nm) leading to less
parasitic L and C, and thereby faster switching rates. This phenomenon also
is apparent in RAMs, ROMs, ASICs, and gate arrays. This leads to PCBs
requiring terminators, new CAD routing disciplines, and component additions
to minimize ground bounce effects. More and more designs are requiring these
faster devices to meet more demanding specifications that match or beat the
competition. The following one-day courses
provide great instruction in high-speed digital design/EMI: ·
Transmission
Lines ·
Crosstalk,
Layer Stacking, Separating Analog/Digital Planes, and Terminations ·
Bypassing,
Power Delivery, Vias, Connectors, and Buses ·
Differential
Signaling and Clock Distribution Control ·
Key
Issues for EMI/EMC: How to Design and Build a Compliant System These
courses provide participants with the tools for recognizing the problems with
any proposed high-speed design. Design rules and design processes are taught
that insure the PCB will function properly at the prototype stage. Emphasis
is placed on cost-competitive design without sacrificing high-speed
integrity. The
courses are intended for digital design engineers, design managers, test
engineers, EMI/EMC engineers, IC digital logic
designers, project managers of high-speed designs, communication engineers,
and military digital engineers. No advanced math is required, although
participants will find it helpful to bring a scientific calculator to the
course. The material is presented at a technical level that provides
experienced designers with information to design and lay out a high-speed PCB
that meets signal integrity (SI) and EMI. Each
course may be taken on a stand-alone basis or combined as needed. While each subsequent
course builds upon the previous instruction, participants may enroll in any
course or combination. Transmission Lines One Day Course Course Program Fundamentals ·
Frequency,
time, and distance ·
Lumped
versus distributed systems ·
EM
fields ·
Geometry,
C, L, and Zo interrelationships ·
C&L
resonance High-Speed Properties
of Logic Gates ·
Quiescent
versus active dissipation ·
Driving
capacitive loads ·
Input
power and external power ·
TTL,
CMOS, SiGe, In Ph, ECL,
and GaAs; output power, speed and engineering disciplines,
Dv, di effects and voltage margins ·
Intersymbol Interference (ISI), eye diagrams and jitter ·
Shoot
Through Current (SSO) and how to minimize it ·
Ground
bounce, lead inductance, Simultaneous Switching Noise (SSN) ·
Viewing
a serial data transmission system, the eye pattern closure: ISI, skin effect,
and tan loss ·
PLL
and DLLs Transmission Line
Characteristics ·
The
quality factor, Q, and why lumped circuits can ring and cause EMI ·
Infinite
uniform transmission line ·
Effects
of source and load impedance ·
Special
transmission line cases ·
Determining
line impedance and propagation delay using TDR and VNA ·
Skin/proximity
effect and dielectric loss ·
The
capacitive load: Zo and propagation
delay ·
Matching
Zo with trace alturations
(neckdowns): minimizing the C load ·
90o,
45o bends: are they concerns? ·
Characteristics
of T. lines: coax, pair, micro strip, buried micro strip, stripline
and differential: asymmetric, dual, edge Crosstalk, Layer Stacking, Separating Analog/Digital Planes, and
Terminations One Day Course Course Program Ground Planes and
Layer Stacking ·
High-speed
current follows the path of least inductance ·
Crosstalk
in solid and slotted ground planes ·
Inductive/capacitive
ratios for micro strips, striplines, and
asymmetric, dual, and edge differentials ·
Guard
traces: do they stop crosstalk, can they resonate? ·
Near-end
and far-end crosstalk ·
Separating
analog from ECL/PECL and TTL/CMOS the concept of moats/floats/drawbridge ·
Split
planes: CMOS/TTL, PECL, and analog using the same bias voltages ·
How
to stack printed circuit board layers (e.g., 4, 6, and 10 layer) for Zo and crosstalk control, Cu fills on signal
layers, minimizing warpage ·
Interplane
capacitance: how thin, what material and stackup
placement? ·
SIR
vs. frequency, software for performing crosstalk and ground bounce tests Terminations ·
End/source/middle
terminators ·
AC
biasing for end terminators, where should it be used and how to choose the
capacitor ·
Hairball
networks, bifurcated lines, and capactive stubs ·
Terminating
differentials: eliminating common mode and minimizing power ·
What
causes differentials unbalance? ·
Diode
and active terminators, resistor selection, and crosstalk in terminators Bypassing, Power Delivery, Vias,
Connectors, and Buses One Day Course Course Program Power Systems ·
Providing
a stable voltage reference: Cu planes ·
Distributing
uniform voltage: sense lines, bulk C, and interplane
C ·
Choosing
a bypass capacitor: electrolytic/tantalum and ceramic ·
Power
plane resonance: serial and parallel, how to minimize both ·
Designing
a .1 ohm bypass system up to Fknee ·
Designing
for constant ESR ·
IC
die capacitance, discrete C in the IC package ·
Why
the 0201: both for better bypassing and EMI control ·
Minimizing
L-capacitor layouts for SOICs, PLCCs, and various configurations of BGAs ·
Layout
requirements for power delivery Vias ·
Mechanical
properties of vias ·
Capacitance
and inductance of vias ·
Return
current and its relation to vias ·
Through
hole, blind, buried, micro vias ·
Intelligent
vias and autorouters ·
Via
discontinuity and via resonance concerns Connectors and Cables ·
Mutual
and series inductance: how connectors create crosstalk ·
Using
connectors on a multidrop bus (Z mismatch
reflection) and how to match Zc to Zo ·
Measuring
coupling in a connector ·
Continuity
of Gnd underneath a connector ·
Special
connectors for high-speed requirements: crosstalk and matching Zo ·
Matching
signaling through a connector (impedance discontinuity) Buses ·
Multidrop
systems: drivers, transceivers, and designing a high-speed bus ·
How
they function, clock rates, typical failures ·
ISI:
minimize the effect with equalization and preemphasis ·
LVDS:
types, unbalance, noise, layout, and making them function ·
Methods
to speed up busses: distributive driving and load capacitance matching Differential Signaling and Clock Distribution Control One Day
Course Course Program Differential
Signaling ·
Attributes/drawbacks
of loosely/tightly coupled differential pairs ·
Definition
and examples of differential and common mode V and I ·
Differential
impedance: odd and even modes ·
Advantages
and disadvantages of edge (side by side), broadside (dual), asymmetric, and microstrip differentials ·
Reflections
and crosstalk in differentials; metastability, Clk skew, driver skew, bit pattern sensitivity, ISI, skin
effect, and dielectric constant; jitter, BER, and the eye diagram ·
Matching
electrical lengths Clock Distribution ·
Timing
margin and clock skew ·
Using
low-impedance drivers and clock distribution lines ·
Source
termination of multiple clock lines ·
Controlling
crosstalk on clock lines ·
Delay
adjustments: serpentine traces/DACs and varactors
for dynamic delay ·
Differential
distribution ·
Controlling
clock signal duty cycle using the integrator ·
Source
synchronous clocking, DDR and RDRAM High-Speed Clocking ·
Clock
skew and jitter ·
PLLs,
DDLs, serpentine traces, and programmable delays ·
Source
and end termination considerations for star, daisy chain, and driving
multiple loads ·
Pre-emphasis
and equalization techniques ·
The
effects of ISI, skin, and dielectric losses ·
The
effect of various base materials of long-haul transmission; the effects of
eye closure on BER ·
A
real-world example of compensation techniques Key Issues for EMI/EMC: How to Design and Build a Compliant
System One Day Course If
you are a design engineer, it pays to know how and why EMI testing is
conducted, as well as the typical causes of failure. This course provides
ways to prevent common EMI/EMC problems regarding power supplies, cables,
connectors, slots, discontinuity of ground planes, and more. The focus is on
EMI and RFI issues regarding PCBs as well as relevant EMI regulations in the This
course covers the following topics: how the EMI/EMC tests are conducted and
how to avoid many configuration layout problems; design techniques to
minimize radiation/susceptibility for both digital and analog PCBs; grounding
and shielding techniques; and how to overcome radiation problems with
connectors, cables, and hardware slots. Course Program EMI, Source, Path,
and Receptor ·
Why
all three must be present to have an EMI problem ·
EMI
regulations/standards for ·
Course
notes provide a detailed description of all the test requirements, equipment
to conduct the tests, and the governing bodies/committees that mandate the
tests Threats ·
RFI ·
ESD ·
Power
Disturbances ·
Internal EMI Issues ·
Frequency ·
Amplitude ·
Time ·
Impedance
dimensions EMI Regulations ·
Commercial ·
Military ·
Avionics ·
Automotive ·
Medical ·
Communications Conducting an EMI
Test ·
Precompliance, compliance testing, and post-audit testing ·
What
is uncertainty and how does it affect the test plan? How Tests are
Conducted For
all of the following tests, the hardware instrumentation, layout, pass/fail criteria,
and tips/techniques to pass the test are covered. The test site also is
defined, i.e., OATS, screen room, anechoic chamber, and TEM cell. The
step-by-step sequence of how each test is conducted is detailed. ·
Conducted
emissions ·
Radiated
emissions ·
RF
immunity ·
Conducted
RF immunity ·
ESD ·
Lightening ·
Electrical
fast transient These courses include the following for each
student: ·
Instruction covering the most critical and
salient aspects of the subject addressed
·
Comprehensive class notes that can be redlined
by and for four of the courses, books
·
Exhibits for viewing in most of the
courses ·
Certificates of completion. Costs for Mr. Hanson’s Seminars The cost for Mr. Hanson’s seminars includes texts,
supplementary notes, and all training. Mr. Hanson pays for his own travel.
With Mr. Hanson at your location, you avoid the hassle and cost of travel.
EUROPE OR For other locations
outside of the United States-Canada-Mexico, contact us. The prices above are the total cost; Mr. Hanson pays
for his own travel expenses. Request a Private, on-site seminar using our online form E-mail us
to request a private, on-site seminar Please include your name, address of the proposed on-site seminar, proposed dates, and any other relevant information. Comments about the web pages, contact Jim
Hanson at hansonjb@gmail.com
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Americom
Seminars provides exceloin us at an Americom Seminar! Comments about
the web pages, contact Jim Hanson at hansonjb@gmail.com |